This invention relates to array processors in general and more particularly to a cellular array processor having a highly parallel, highly regular design with a single instruction multiple data (SIMD) architecture.
In the present state of the technology associative processors or array processors have been widely investigated. Essentially, such a processor constitutes a plurality of individual processing cells arranged in a matrix. This combination of processing cells is able to be programmed to enable the solution of complex mathematical problems. There have been many excellent articles in the literature which relate to various forms of such processors.
For example reference is made to an article which appeared in the June 1985 issue of IEEE COMPUTER. This article is entitled "Multiprocessing Technology" by Chuan-Lian Wu. A further article appeared in HIGH TECHNOLOGY, July 1985 on pages 20-28 entitled "Parallel Processing Gets Down to Business " by E. J. Lerner.
Such processors while capable of performing and solving complicated problems are attendent with many different characteristics and requirements. Many present processors employ the single instruction, single data architecture. This particular architecture is well suited for regular applications. It is inherently highly structured and can be configured into different sizes without much additional cost.
In regard to such a structure, the SIMD architecture is highly regular, the data elements are processed in large blocks, the volume of the input data is very large and the desired response time may be very short and critical as the computation requirements per datum are relatively uniform. Within SIMD machines there are both array processors and cellular array processors. Array processors generally have a high performance pipeline of arithmetic elements, little parallelism, and operate upon an array of data.
A cellular array processor is highly parallel having an array of processors each operating upon an array of data. This multiplicity of processors benefits very well from highly structured VLSI design, especially as extended by fault tolerance techniques to be described.
As indicated, the prior art has provided numerous types of array processors. In any event, there are only a few cellular array processors. One such device is manufactured by Goodyear and designated as the MPP. See an article entitled "Design Of A Massively Parallel Processor" which appeared in the IEEE COMPUTER SOCIETY, 1980, pages 80 to 85 by K. E. Butcher. This article describes a cellular array processor.
Such processors operate on storing data streams and processing data streams. The above described processor is designed to operate on a bit serial, word parallel fashion. Each word is stored one bit after another through a succession of memory locations. In any event, this provides for increased operating time while presenting a number of problems in construction. Hence the processor to be described in this application operates in a bit parallel, word parallel manner and, therefore, has more flexibility in memory addressing and allows one to program the same in a simpler and efficient manner.